1. Field of Invention
The present invention relates to a method of fabricating a multi-level interconnect of a semiconductor feature. More particularly, the invention relates to a method of fabricating a copper (Cu) damascene and a Cu dual damascene.
2. Description of Related Art
It was known that the semiconductor manufacture has entered the deep sub-micron process. In addition to a reduction of the transistor size to increase the device operation speed in such process, the operation speed and reliability of the device can be further increased by manufacturing the device with different materials.
In the backend process of the semiconductor device, the current RC time delay in a metal line has gradually increased as the width of the metal line is reduced. This may easily produce an electron migration (EM) effect in the conventional metal line formed mainly of aluminum (Al), therefore reducing the reliability of the device.
To resolve the above problems encountered by the semiconductor device in the deep sub-micron process, copper (Cu) with a lower resistance and minimum EM effect is adopted and has thus become the uniform choice for all semiconductor device manufacturers.
However, as Cu is not easily etched with common etching gases, a Cu metal line would not be manufactured by a conventional method. A Cu damascene process is therefore proposed.
FIGS. 1A to 1F are schematic diagrams showing the process flow for fabricating a conventional Cu dual damascene.
Referring to FIG. 1A, a silicon oxide (SiO.sub.x) layer 102 is formed to cover a substrate 100. A silicon nitride (SiN.sub.x) layer 104 is then formed to cover the SiO.sub.x layer 102, while a SiO.sub.x layer 106 is further formed to cover this SiN.sub.x layer 104.
The SiO.sub.x layer 102, the SiN.sub.x layer 104, and the SiO.sub.x layer 106 are made into an inter-metal dielectric layer (IMD layer) in which the method may involve a plasma enhanced chemical vapor deposition (PECVD).
Referring to FIG. 1B, a trench line 108 is formed in the SiO.sub.x layer 106 by photolithography and etching. In the defining process for the trench line 108, the SiN.sub.x layer 104 is used as an etching stop layer to prevent the over etching during the formation of the trench line 108.
Referring to FIG. 1C, the SiN.sub.x layer 104 and the SiO.sub.x layer 102 located at a bottom of the trench line 108 are defined by further photolithography and etching, so that a via 110 is formed at the bottom of the trench line 108.
Referring to FIG. 1D, a barrier layer 112 and a Cu layer 114 are formed in sequence to cover the trench line 108, the via 110, and the SiO.sub.x layer 106. The barrier layer 112 and the Cu layer 114 may be formed by physical vapor deposition (PVD) or CVD.
Referring to FIG. 1E, a Cu electroplating is performed, with the Cu layer 114 serving as a seeding layer, to form a Cu layer 116 that covers the Cu layer 114.
Referring to FIG. 1F, the barrier layer 112 and the Cu layers 114, 116, which layers cover a top surface of the SiO.sub.x layer 106 are removed, so that only a barrier layer 112a and Cu layers 114a, 116a remain in the trench line 108 and the via 110.
The method for removing the barrier layer 112 and the Cu layers 114, 116 that cover the top surface of the SiO.sub.x layer 106 may involve chemical mechanical polishing (CMP).
With the continuing shrinkage of the device size, it is not easy to maintain an excellent conformity of a Cu seeding layer in a structure with a high aspect ratio by PVD.
Furthermore, the Cu seeding layer formed by CVD has a poor quality for its film, while the cost for manufacturing the Cu layer by CVD is very high.
As it is necessary to form the Cu seeding layer by PVD or CVD using additional machines, the cost to perform the conventional fabricating method is higher.